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quad-channel, 2.5 kv isolators with integrated dc-to-dc converter data sheet adum5401 / adum5402 / adum5403 / adum5404 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2012 analog devices, inc. all rights reserved. features iso power integrated, isolated dc-to-dc converter regulated 3.3 v or 5.0 v output up to 500 mw output power quad dc-to-25 mbps (nrz) signal isolation channels 16-lead soic package with 7.6 mm creepage high temperature operation: 105c maximum high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity (pending) iec 60747-5-2 (vde 0884, part 2) v iorm = 560 v peak applications rs-232/rs-422/rs-485 transceivers industrial field bus isolation power supply start-up bias and gate drives isolated sensor interfaces industrial plcs general description the adum5401 / adum5402/ adum5403/ adum5404 1 are quad-channel digital isolators with iso power?, an integrated, isolated dc-to-dc converter. based on the analog devices, inc., i coupler? technology, the dc-to-dc converter provides up to 500 mw of regulated, isolated power at either 5.0 v or 3.3 v from a 5.0 v input supply, or at 3.3 v from a 3.3 v supply at the power levels shown in table 1. these devices eliminate the need for a separate, isolated dc-to-dc converter in low power, isolated designs. the i coupler chip scale transformer technology is used to isolate the logic signals and for the power and feedback paths in the dc-to-dc converter. the result is a small form factor, total isolation solution. the adum5401 / adum5402/ adum5403/ adum5404 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. see the an-0971 application note for board layout recommendations. functional block diagrams 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 4 channel i coupler core v dd1 reg gnd 1 v ia /v oa v ib /v ob v ic /v oc v od rc out gnd 1 v iso gnd iso v oa /v ia v ob /v ib v oc /v ic v id v sel gnd iso adum5401/adum5402/ adum5403/adum5404 06577-001 figure 1. 3 4 5 6 14 13 12 11 adum5401 06577-100 v ia v ib v oa v ob v ic v oc v od v id figure 2. adum5401 3 4 5 6 14 13 12 11 adum5402 06577-101 v ia v ib v oa v ob v oc v ic v od v id figure 3. adum5402 3 4 5 6 14 13 12 11 adum5403 06577-102 v ia v ob v oa v ib v oc v ic v od v id figure 4. adum5403 3 4 5 6 14 13 12 11 adum5404 06577-103 v oa v ob v ia v ib v oc v ic v od v id figure 5. adum5404 table 1. power levels input voltage (v) output voltage (v) output power (mw) 5.0 5.0 500 5.0 3.3 330 3.3 3.3 200 1 protected by u.s. patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. othe r patents are pending.
adum5401/adum5402/ad um5403/adum5404 data sheet rev. c | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? electrical characteristics5 v primary input supply/ 5 v secondary isolated supply ................................................... 4 ? electrical characteristics3.3 v primary input supply/ 3.3 v secondary isolated supply ................................................ 6 ? electrical characteristics5 v primary input supply/ 3.3 v secondary isolated supply ................................................ 8 ? package characteristics ............................................................. 10 ? regulatory information ............................................................. 10 ? insulation and safety-related specifications .......................... 10 ? iec 60747-5-2 (vde 0884, part 2):2003-01 insulation characteristics ............................................................................ 11 ? recommended operating conditions .................................... 11 ? absolute maximum ratings .......................................................... 12 ? esd caution ................................................................................ 12 ? pin configurations and function descriptions ......................... 13 ? truth table .................................................................................. 16 ? typical performance characteristics ........................................... 17 ? terminology .................................................................................... 20 ? applications information .............................................................. 21 ? pcb layout ................................................................................. 21 ? thermal analysis ....................................................................... 21 ? propagation delay-related parameters ................................... 22 ? start-up behavior....................................................................... 22 ? emi considerations ................................................................... 22 ? dc correctness and magnetic field immunity .......................... 22 ? power consumption .................................................................. 23 ? power considerations ................................................................ 24 ? increasing available power ....................................................... 24 ? insulation lifetime ..................................................................... 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 3 of 28 revision history 6/12rev. b to rev. c created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 updated outline dimensions ........................................................ 26 9/11rev. a to rev. b changes to product title, features section, and general description section ........................................................................... 1 added table 1; renumbered sequentially ..................................... 1 changes to specifications section ................................................... 3 changes to table 19 and table 20 ................................................. 11 changes to table 21 ........................................................................ 12 changes to table 22 ........................................................................ 13 changes to table 23 ........................................................................ 14 changes to table 24 and table 25 ................................................. 15 changes to figure 11 to figure 13 ................................................ 16 changes to figure 11, figure 12 caption, figure 14 caption, and figure 16 caption .................................................................... 16 added figure 19 and figure 20; renumbered sequentially ...... 17 changes to figure 21 and figure 22 ............................................. 17 changes to terminology section .................................................. 19 changes to applications information section ............................ 20 deleted increasing available power, figure 15, and figure 16; renumbered sequentially .............................................................. 20 changes to pcb layout section .................................................... 20 added start-up behavior section ................................................. 21 moved and changes to emi considerations section ................ 21 changes to dc correctness and magnetic field immunity section .............................................................................................. 21 changes to power consumption section and figure 29 ........... 22 changes to power considerations ................................................ 23 added increasing available power section and table 26 .......... 23 added table 27 ................................................................................ 24 changes to insulation lifetime section ....................................... 24 11/08rev. 0 to rev. a changes to figure 1 and general description section ................ 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 4 ............................................................................ 7 changes to table 6 and table 7 ....................................................... 8 changes to table 8 and table 9 ....................................................... 9 changes to figure 7 and table 10 ................................................. 10 changes to figure 8 and table 11 ................................................. 11 changes to figure 9 and table 12 ................................................. 12 changes to figure 10 and table 13 ............................................... 13 moved truth table section ............................................................ 13 changes to applications information section and pcb layout section .............................................................................................. 17 changes to dc correctness and magnetic field immunity section .............................................................................................. 18 changes to power considerations section .................................. 20 added increasing available power section, table 15, and table 16 ..................................................................................... 20 5/08revision 0: initial version
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 4 of 28 specifications electrical character istics 5 v primary input su pply/5 v secondary i solated supply t ypical specifications are at t a = 25c, v dd1 = v sel = v iso = 5 v. minimum/maximum specifications apply over the ent ire recommended operation range which is 4.5 v v dd1 , v sel , v iso 5.5 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 2 . dc -to - dc converter static specification s parameter symbol min typ max unit test conditions /comments dc - to - dc converter supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso (load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso (rip) 75 mv p -p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 90 ma output noise v iso (n oise ) 200 mv p -p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz output supply current i iso (max) 100 ma v iso > 4.5 v efficiency at i iso (max) 34 % i iso = 100 ma i dd1 , no v iso load i dd1 (q) 19 30 ma i dd1 , full v iso load i dd1 (max) 290 ma table 3 . dc -to - dc converter dynamic specifications paramet er symbol 1 mbps a grade, c grade 25 mbps c grade unit test conditions/comments min typ max min typ max supply current i nput i dd1 adum5401 19 68 ma no v iso load adum5402 19 71 ma no v iso load adum5403 19 75 ma no v iso load adum5404 19 78 ma no v iso load available to load i iso (load) adum5401 100 87 ma adum5402 100 85 ma adum5403 100 83 ma adum5404 100 81 ma table 4 . switching specifications parameter symbol a grade c grade unit test conditions/comments min typ max min typ max switching specifications data rat e 1 25 mbps within pwd limit propagation delay t phl , t plh 55 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 15 ns between any two units channel matchi ng codirectional 1 t pskcd 50 6 ns opposing direction al 2 t pskod 5 0 15 ns 1 7 codirectional channel matching is the absolute va lue of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 5 of 28 table 5. input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold v il 0.3 v iso or 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0.3 or v iso ? 0.3 5.0 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v ddl , v iso supplies positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i i ?20 +0.01 +20 a 0 v v ix v ddx ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.7 v dd1 or 0.7 v iso for a high output or v o < 0.3 v dd1 or 0.3 v iso for a low output. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 6 of 28 electrical character istics 3.3 v primary input supp ly/ 3.3 v secondary isolated supply t ypical specifications are at t a = 25c, v dd1 = v iso = 3.3 v , v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range which is 3.0 v v dd1 , v sel , v iso 3.6 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 6 . dc -to - dc converter static specification s pa rameter symbol min typ max unit test conditions/comments dc - to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 30 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 ma to 54 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 54 ma output noise v iso (noise) 130 mv p -p c bo = 0.1 f||10 f, i iso = 54 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz output supply cur rent i iso (max) 60 ma v iso > 3 v efficiency at i iso (max) 3 3 % i iso = 60 ma i dd1 , no v iso load i dd1 (q) 14 20 ma i dd1 , full v iso load i dd1 (max) 175 ma table 7 . dc -to - dc converter dynamic specifications parameter symb ol 1 mbps a or c grade 25 mbps c grade unit test conditions/comments min typ max min typ max supply current i nput i dd1 adum5401 14 44 ma no v iso load adum5402 14 46 ma no v iso load adum5403 14 47 ma no v iso load adum5404 14 51 ma no v iso load available to load i iso (load ) adum5401 60 52 ma adum5402 60 5 1 ma adum5403 60 4 9 ma adum5404 60 4 8 ma table 8 . switching specifications parameter symbol a grade c grade unit test conditions/comments min typ max min typ max switching specifications data rate 1 25 m bps within pwd limit propagation delay t phl , t plh 60 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 45 ns between any two units channel matching codirectional 1 t pskcd 50 6 ns opposing directional 2 t pskod 50 15 ns 1 7 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 7 of 28 table 9 . input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold v il 0.3 v iso or 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0. 3 or v iso ? 0.3 3.3 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 3.1 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v d dl , v iso s upplies positive going threshold v uv+ 2.7 v negative going threshold v uv ? 2.4 v hystere sis v uvh 0.3 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v dd x ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustaine d while maintaining v o > 0. 7 v dd1 or 0. 7 v iso for a high out put or v o < 0. 3 v dd1 or 0. 3 v iso for a low output. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 8 of 28 electrical character istics 5 v primary input supp ly/ 3.3 v secondary isolated suppl y t ypical specifications are at t a = 25c, v dd1 = 5.0 v, v iso = 3.3 v , v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range which is 4.5 v v dd1 5.5 v , 3.0 v v iso 3.6 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 10. dc -to - dc converter static spe cification s parameter symbol min typ max unit test conditions/comments dc - to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 ma to 54 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 90 ma output noise v iso (n oise ) 130 mv p -p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz o utput supply current i iso (max) 100 ma v iso > 3 v efficiency at i iso (max) 3 0 % i iso = 9 0 ma i dd1 , no v iso load i dd1 (q) 14 20 ma i dd1 , full v iso load i dd1 (max) 230 ma table 11. dc -to - dc converter dynamic specificati ons parameter symbol 1 mbps a or c grade 25 mbps c grade unit test conditions/comments min typ max min typ max supply current i nput i dd1 adum5401 9 44 ma no v iso load adum5402 9 45 ma no v iso load adum5403 9 46 ma no v iso load adum5404 9 47 ma no v iso load available to l oad i iso (load) adum5401 100 92 ma adum5402 100 91 ma adum5403 100 89 ma adum5404 100 88 ma table 12 . switching specifications parameter symbol a grade c grade unit test conditions/comments min typ max min typ max switching specifications dat a rat e 1 25 mbps within pwd limit propagation delay t phl , t plh 60 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 15 ns between any two units channel matching codirectional 1 t pskcd 50 6 ns opposing directional 2 t pskod 50 15 ns 1 codirectional channel matching is the ab solute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two chann els with inputs on opposing sides of the isolation barrier.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 9 of 28 table 13. input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold v il 0.3 v iso or 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0.2 , v iso ? 0.2 v dd1 or v iso v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 v dd1 ? 0.2 or v iso ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervolt age lockout uvlo v dd1 , v ddl , v iso s upplies positive going threshold v uv+ 2.7 v negative going threshold v uv ? 2.4 v hyster e sis v uvh 0.3 v input currents per channel i i ?10 +0.01 +10 a 0 v v i x v dd x ac specifications output rise /fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient m agnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0. 7 v dd1 or 0. 7 v iso for a high out put or v o < 0. 3 v dd1 or 0. 3 v iso for a low output. the c ommon - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 10 of 28 package characterist ics table 14. parameter sym bol min typ max unit test conditions/comments resistance and capacitance resistance (input -to - output) 1 r i - o 10 12 ? capacitance (input -to - output) 1 c i - o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 3 1 this device is considered a 2 - terminal device; pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the thermal analysis section for thermal model definitions. regulatory information the adum5401 / adum5402 / adum5403 / adum5404 are approved by the organizations listed in table 15 . refer to table 20 and the insulation lifetime section for more information about the recommended maximum working voltages for specific cross - insulation waveforms and insulation levels. table 15. ul 1 csa vde (pending) 2 recognized under 1577 component reco g nition program 1 approved under csa component acceptance notice #5a certified according to iec 60747- 5 -2 (vde 0884 part 2):2003 -01 2 single protection, 2500 v rms isolation voltage testing was conducted per csa 60950 - 1 - 07 and iec 60950 -1 2 nd ed. at 2.5 kv rated voltage basic insulation at 600 v r ms (848 v peak) working voltage reinforced insulation at 250 v rms (353 v peak) working voltage basic insulation, 560 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum5401 / adum5402 / adum5403 / adum5404 is proof tested by applying an insulation test voltage 3 000 v rms for 1 second (current leakage det ection limit = 10 a). 2 i n accordance with iec 60747 - 5 - 2 (vde 0884 part 2):2003 - 01 , each adum5401 / adum5402 / adum5403 / adum5404 is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marking branded on the component designates iec 60747 - 5 - 2 (vde 0884 part 2):2003 - 01 approval. insulati on and safety - related specificatio ns table 16. critical safety - related dimensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1 - minute duration minim um external air distance l(i01) 8.0 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7. 6 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti > 175 v din iec 112/vde 0303, part 1 material group i i ia material g roup (din vde 0110, 1/89, table 1)
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 11 of 28 iec 60 747 - 5 - 2 (vde 0884, part 2) :2003 - 01 insulation charac teristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by the protective circuits. the asterisk (*) marking branded on the package denotes iec 60747 - 5 - 2 (vde 0884, part 2) approval. table 17. vde characteristics description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pr , 100% pro duction test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input - t o - output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 s ec, partial discharge < 5 pc 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v tr 4000 v peak safe ty limiting values maximum value allowed in the event of a failure (see figure 6 ) case temperature t s 150 c side 1 i dd1 current i s1 555 ma insulation resistance at t s v io = 500 v r s >10 9 ? 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 06577-002 figure 6 . thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747 - 5- 2 recommended operatin g conditions table 18. parameter symbol min max unit operating temperature 1 t a ?40 + 105 c supply voltages 2 v dd1 @ v sel = 0 v v dd 3.0 5.5 v v dd1 @ v sel = v iso v dd 4.5 5.5 v 1 operation at 105c requires reduction of the maximum load current as spe cified in table 19. 2 each voltage is relative to its respective ground.
adum5401/adum5402/ad um5403/adum5404 data sheet rev. c | page 12 of 28 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 19. parameter rating storage temperature range (t st ) ?55c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltages (v dd1 , v iso ) 1 ?0.5 v to +7.0 v input voltage (v ia , v ib , v ic , v id , v sel ) 1, 2 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob , v oc , v od ) 1, 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 ?10 ma to +10 ma common-mode transients 4 ?100 kv/s to +100 kv/s 1 each voltage is relative to its respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 3 see figure 6 for maximum rated curre nt values for various temperatures. 4 common-mode transients exceeding the absolute maximum slew rate may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 20. maximum continuous working vo ltage supporting 50-year minimum lifetime 1 parameter max unit applicable certification ac voltage, bipolar waveform 424 v peak all certifications, 50-year operation ac voltage, unipolar waveform basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 353 v peak working voltage per iec 60950-1 dc voltage basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 353 v peak working voltage per iec 60950-1 1 refers to the continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime sect ion for more information.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 13 of 28 pin configurations a nd function descript ions v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 1 1 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5401 t op view (not to scale) 06577-004 figure 7. adum540 1 pin configuration table 21. adum540 1 pin function descriptions pin no. mnemonic description 1 v dd1 primary suppl y voltage, 3.0 v t o 5.5 v . 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od lo gic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow the adum5401 to control the regulation of the slave device. 9, 15 gnd iso ground ref erence for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpo int is 3.3 v. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads, 3.3 v (v sel low) or 5.0 v (v sel high).
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 14 of 28 v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 1 1 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5402 t op view (not to scale) 06577-005 figure 8. adum540 2 pin configuration table 22. adum540 2 pin function descriptions pin no. mnemonic description 1 v dd1 primary suppl y voltage, 3.0 v to 5.5 v . 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od lo gic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow th e adum540 2 to control the regulation of the slave device. 9, 15 gnd iso ground ref erence for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpo int is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads, 3.3 v (v sel low) or 5.0 v (v sel high).
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 15 of 28 v dd1 1 gnd 1 2 v ia 3 v ob 4 v iso 16 gnd iso 15 v oa 14 v ib 13 v oc 5 v ic 12 v od 6 v id 1 1 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5403 t op view (not to scale) 06577-006 figure 9. adum540 3 pin configuration table 23. adum540 3 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 v oc logic output c. 6 v od lo gic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allo w the adum5403 to control the regulation of the slave device. 9, 15 gnd iso ground refer ence for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoin t is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads, 3.3 v (v sel low) or 5.0 v (v sel high).
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 16 of 28 v dd1 1 gnd 1 2 v oa 3 v ob 4 v iso 16 gnd iso 15 v ia 14 v ib 13 v oc 5 v ic 12 v od 6 v id 1 1 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5404 t op view (not to scale) 06577-007 figure 10 . adum5404 pin configuration table 24. adum540 4 pin function descriptions pin no. mnemonic description 1 v dd1 primary su pply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v oa logic output a. 4 v ob logic output b. 5 v oc logic output c. 6 v od logi c output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow the adum5404 to control the regulation of the slave device. 9, 15 gnd iso ground referen ce for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v ia logic input a. 16 v iso secondary supply voltage output for external loads, 3.3 v ( v sel low) or 5.0 v ( v sel high). truth table table 25 . truth table (positive logic) v sel 1 rc out 2 v dd1 (v) v iso (v) notes h pwm 5 5 master mode, normal operation l pwm 5 3.3 master mode, normal operation l pwm 3.3 3.3 master mode, normal operation h pwm 3.3 5 this supply configuration is not recommended due to ex tremely poor efficiency 1 h refers to a high logic, and l refers to a low logic. 2 pwm refers to the regulation control signal. this signal is derived from the secondary side regulator and can be used to cont rol other iso power devices.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 17 of 28 typical performance characteristics 0 5 10 15 20 25 30 35 40 0 0.02 0.04 0.06 0.08 0.10 0.12 06577-033 output current (a) efficienc y (%) 3.3v input/3.3v output 5v input/3.3v output 5v input/5v output figure 11 . typical power supply efficiency at 5 v input/5 v outp ut and 3.3 v input/3.3 v output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.02 0.04 0.06 0.08 0.10 0.12 i iso (a) power dissi pa tion (w) v dd1 = 5 v , v iso = 5v v dd1 = 5 v , v iso = 3.3v v dd1 = 3.3 v , v iso = 3.3v 06577-026 figure 12 . typical total power dissipa tion vs. isolated output supply current in all supported power configuration s 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input current (a) output current (a) 06577-027 3.3v input/3.3v output 5v input/3.3v output 5v input/5v output figure 13 . typical isolated output supply current vs. input current in all supported power configuration s 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 6 . 5 i n p u t s u pp l y v o l t a g e ( v ) p o w e r ( w ) i d d 0 65 77 - 0 1 1 i n p u t c u rr e n t ( a ) p o we r figure 14 . ty pical short - circuit input current and power vs. v dd1 supply voltage 06577-012 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 15 . typical v iso transient load response, 5 v output, 10% to 90% load step 06577-013 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 16 . typical v iso transient load respons e, 3 .3 v output, 10% to 90% load step
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 18 of 28 06577-014 bw = 20mhz (400ns/div) 5v output ripple (10mv/div) figure 17 . typical v iso = 5 v output voltage ripple at 90% load 06577-015 bw = 20mhz (400ns/div) 3.3v output ripple (10mv/div) figure 18 . typical v iso = 3.3 v output voltage ripple at 90% load 06577-030 time (ms) v iso (v) 7 6 5 4 3 2 1 0 ?1 0 1 2 3 90% load 10% load figure 19 . typical output voltage start - u p transient at 10% and 90% load , v iso = 5 v 06577-031 time (ms) v iso (v) 5 4 3 2 1 0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 90% load 10% load figure 20 . typical output voltage start - u p transient at 10% and 90% load , v iso = 3.3 v 0 4 8 1 2 1 6 2 0 0 5 1 0 1 5 d at a r a te (mbps) supp l y current (ma) 2 0 2 5 06577-028 5v input/5v output 3.3v input/3.3v output 5v input/3.3v output figure 21 . typical i ch s upply current per forward data channel (15 pf output load) 0 4 8 1 2 1 6 2 0 0 5 1 0 1 5 data rate (mbps) supply current (ma) 2 0 2 5 5v input/5v output 3.3v input/3.3v output 5v input/3.3v output 06577-029 figure 22 . typical i ch supply current per reverse data channel (15 pf output load)
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 19 of 28 0 5 10 15 da ta ra te (m bp s) supply current (ma) 20 25 5v 3.3v 06 5 77 - 11 9 0 2 1 3 4 5 figure 23 . typical i iso (d) dynamic supply current per input 0 1.0 0.5 1.5 2.0 2.5 3.0 0 5 10 15 da ta ra te (m bp s) supply current (ma) 20 25 5v 3.3v 06 5 77 - 11 8 figure 24 . typical i iso (d) dynamic supply current per output (15 pf output load)
adum5401/adum5402/ad um5403/adum5404 data sheet rev. c | page 20 of 28 terminology i dd1 (q) i dd1 (q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1 (q) reflects the minimum current operating condition. i dd1 (d) i dd1 (d) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1 (max) i dd1 (max) is the input current under full dynamic and v iso load conditions. i so (load) i so (load) is the current available to the load. t phl propagation delay the t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew, t psk t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temper- ature, supply voltages, and output load within the recommended operating conditions. channel-to-channel matching, (t pskcd /t pskod ) channel-to-channel matching is the absolute value of the difference in propagation delays between two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 21 of 28 applications information the dc-to-dc converter section of the adum5401 / adum5402/ adum5403/ adum5404 works on principles that are common to most switching power supplies. it has a secondary side controller architecture with isolated pulse-width modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip scale air core transformer. power transferred to the secondary side is rectified and regulated to either 3.3 v or 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the adum5401 / adum5402 / adum5403 / adum5404 implement undervoltage lockout (uvlo) with hysteresis on the v dd1 power input. this feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. pcb layout the adum5401 / adum5402/ adum5403/ adum5404 digital isolators with 0.5 w iso power integrated dc-to-dc converter require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 25). note that low esr bypass capacitors are required between pin 1 and pin 2 and between pin 15 and pin 16, as close to the chip pads as possible. the power supply section of the adum5401/ adum5402/ adum5403/ adum5404 uses a 180 mhz oscillator frequency to pass power efficiently through its chip scale transformers. in addition, the normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. these are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 and v iso . the smaller capacitor must have a low esr; for example, use of a ceramic capacitor is advised. the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. consider bypassing between pin 1 and pin 8 and between pin 9 and pin 16 unless both common ground pins are connected together close to the package. v dd1 gnd 1 v ia /v oa v ib /v ob v iso gnd iso v oa /v ia v ob /v ib v ic /v oc v oc /v ic v od rc out v id v sel gnd 1 bypass < 2mm gnd iso 06577-120 figure 25. recommended pcb layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device as specified in table 19, thereby leading to latch-up and/or permanent damage. the adum5401 / adum5402 / adum5403 / adum5404 are power devices that dissipate approximately 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the pcb through the gnd pins. if the devices are used at high ambient temperatures, provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 25 shows enlarged pads for pin 8 and pin 9. large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. the dimensions of the expanded pads are at the discretion of the designer and depend on the available board space. thermal analysis the adum5401 / adum5402/ adum5403/ adum5404 parts consist of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the ja from table 14. the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4-layer board with fine width traces and still air. under normal operating conditions, the adum5401 / adum5402 / adum5403/ adum5404 devices operate at full load across the full temperature range without derating the output current. however, following the recommendations in the pcb layout section decreases thermal resistance to the pcb, allowing increased thermal margins in high ambient temperatures.
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 22 of 28 propagation delay - related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 26 ). the propagation delay to a logic low output may differ from the propagation delay to a logic high. input (v ix ) output (v ox ) t plh t phl 50% 50% 06577-018 figure 26 . propagation delay parameters pulse width distorti on is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel - to - channel matching refers to the maximum amount the propagation delay differs between channels w ithin a single adum5401 / adum5402 / adum5403 / adum5404 component. pr opagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5401 / adum5402 / adum5403 / adum5404 components operating under the same conditions. start - u p behavior the adum5401 / adum5402 / adum5403 / adum5404 do not contain a soft start circuit. therefore, the start - up current and voltage behavior must be taken into account when designing with this de vice. when power is applied to v dd1 , the input switching circuit begins to operate and draw current when the uvlo minimum voltage is reached. the switching circuit drives the maximum available power to the output until it reaches the regulation voltage whe re pwm control begins. the amount of current and the time required to reach regulation voltage depends on the load and the v dd1 slew rate. with a fast v dd1 slew rate (200 s or less), the peak current draws up to 100 ma/v of v dd1 . the input voltage goes hi gh faster than the output can turn on , so the peak current is proportion al to the maximum input voltage. with a slow v dd1 slew rate (in the millisecond range), the input voltage is not changing quickly when v dd1 reaches the uvlo minimum voltage. the curren t surge is approximately 300 ma because v dd1 is nearly constant at the 2.7 v uvlo voltage. the behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short - circuit current shown in figure 14. w hen starting the device for v iso = 5 v operation , d o not limit the current available to the v dd1 power pin to less than 300 ma. the adum5401 / adum5402 / adum5403 / adum5404 device s may not be able to drive the output to the regulation point if a current - limiting device clamps the v dd1 voltage during startup. as a result, the adum5401 / adum5402 / adum5403 / adum5404 d evice s can draw large amounts of current at low voltage for extended periods of time. the output voltage of the adum5401 / adum5402 / adum5403 / adum5404 devices exhibits v iso overshoot during startup. if this overshoot could potentially damage components attached to v iso , a voltage - limiting device such as a zener diode can be used to clamp the voltage. typical behavior is shown in figure 19 and figure 20. emi considerations the dc - to - dc converter section of the adum5401 / adum5402 / adum5403 / adum5404 devices must operate at 180 mhz to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see the an - 0971 application note f or board layout recommend ations dc correctness and m agnetic field immuni ty positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, a periodic set of refresh pulses indicativ e of the correct input state is sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, and the isolator output is forced to a default low state by the watchdog timer circuit. this situation should occur in the adum5401 / adum5402 / adum5403 / adum5404 during powe r - up and power - down operations. the limitation on the magnetic field immunity of the adum5401 / adum5402 / adum5403 / adum5404 is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3.3 v operating condition of the adum5401 / adum5402 / adum5403 / adum5 404 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at approximately 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d /dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). r n is the radius of the n th turn in the receiving coil (cm). n is the total numb er of turns in the receiving coil.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 23 of 28 given the geometry of the receiving coil in the adum5401 / adum5402 / adum5403 / adum5404 , and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 27. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 06577-019 figure 27 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum all owable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receivin g coil. this voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst - case polarity), it reduces the received pulse from >1.0 v t o 0.75 v, still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5401 / adum5402 / adum5403 / adum5404 transformers. figure 28 expresses these allowable curr ent magnitudes as a function of frequency for selected distances. as shown in figure 28 , the adum5401 / adum5402 / adum5403 / adum5404 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz ex ample, a 0.5 ka current placed 5 mm away from the adum5401 / adum5402 / adum5403 / adum5404 is required to affect the operation of the device . magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 06577-020 figure 28 . maximum allowable current for various current - to- adum5401 / adum5402 / adum5403 / adum5404 spacings note that , at combinations of strong magnetic field and high frequency, any loops formed by pcb traces c an induce e rror voltages sufficiently large to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels, as well as to the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined sepa - rately. all of these quiescent power demands have been combined into the i dd1 (q) cur rent, as shown in figure 29 . the total i dd1 supply current is the sum of the quiescent operating current; the dynamic current, i dd1 (d) , demanded by the i/o channels; and any external i iso load. converter prima r y converter seconda r y prima r y dat a input/output 4-channe l i ddp(d) seconda r y dat a input/output 4-channe l i iso(d) i iso i dd1(q) i dd1(d) 06577-024 figure 29 . power consumption within the adum5401 / adum5402 / adum5403 / adum5404 both dynamic input and output current is consumed only when operating at channel speeds higher than the refresh rate, f r . each channel has a dynamic current determined by its data rate . figure 21 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part . figure 22 shows the current for a channel in the reverse direction, which means that the inpu t is on the secondary side of the part. both figures assume a typical 15 pf load. the follow - ing relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 21 or figure 22 , depending on chan nel direction. i iso is the current drawn by the secondary side external load. e is the power supply efficiency at 100 ma load from figure 11 at the v iso and v dd1 condition of interest.
adum5401/adum5402/ad um5403/adum5404 data sheet rev. c | page 24 of 28 the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso (load) = i iso (max) ? i iso (d)n ; n = 1 to 4 (2) where: i iso (load) is the current available to supply an external secondary side load. i iso (max) is the maximum external secondary side load current available at v iso . i iso (d)n is the dynamic load current drawn from v iso by an input or output channel, as shown in figure 23 and figure 24. the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the analysis of i dd1 and i iso (load) . power considerations the adum5401 / adum5402/ adum5403/ adum5404 power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by undervoltage lockout (uvlo) circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. the outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary side power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary side is not being generated. the primary side power oscillator is allowed to free run under these conditions, supplying the maximum amount of power to the secondary side. as the secondary side voltage rises to its regulation setpoint, a large inrush current transient is present at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. the v dd1 current is then reduced and is propor- tional to the load current. the inrush current is less than the short-circuit current shown in figure 14. the duration of the inrush current depends on the v iso loading conditions and on the current and voltage available at the v dd1 pin. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate to the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care that the design allows the converter sufficient time to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo. increasing available power the adum5401 / adum5402/ adum5403/ adum5404 are designed with the capability of running in combination with other compatible iso power devices. the rc out pin allows the adum5401/ adum5402/ adum5403 / adum5404 to provide its pwm signal to another device acting as a master to regulate its self and slave devices. power outputs are combined in parallel while sharing output power equally. the adum5401 / adum5402/ adum5403/ adum5404 can only be a master/standalone, and the adum5200 can only be a slave/ standalone device. the adum5000 can operate as either a master or slave. this means that the adum5000, adum520x , and adum540x can only be used in the master/slave combinations listed in table 26. table 26. allowed combinations of iso power parts slave master adum5000 adum520x adum540x adum5000 yes yes no adum520x no no no adum540x yes yes no the allowed combinations of master and slave configured parts listed in table 26 is sufficient to make any combination of power and channel count.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 25 of 28 table 27 illustrates how iso power devices can provide many combinations of data channel count and multiples of the single unit power. table 27. configurations for power and data channels number of data channels power unit 0 channels 2 channels 4 channels 6 channels 1-unit power adum5000 master adum520x master adum5401 to adum5404 master adum5401 to adum5404 master adum121x 2-unit power adum5000 master adum5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum520x slave adum520x slave adum520x slave 3-unit power adum5000 master adum5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum5000 slave adum5000 slave adum520x slave adum5000 slave adum520x slave adum5000 slave adum5000 slave insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5401/ adum5402/ adum5403/ adum5404 devices. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than the 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum5401/ adum5402 / adum5403/ adum5404 devices depends on the voltage wave- form type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 30, figure 31, and figure 32 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by analog devices. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 20 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. any cross-insulation voltage waveform that does not conform to figure 31 or figure 32 should be treated as a bipolar ac wave- form and its peak voltage limited to the 50-year lifetime voltage value listed in table 20. the voltage presented in figure 32 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 06577-021 figure 30. bipolar ac waveform 0v rated peak voltage 06577-023 figure 31. dc waveform notes: 1. the voltage is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. 0v rated peak voltage 06577-022 figure 32. unipolar ac waveform
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 26 of 28 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.01 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.009 8) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) sea ting plane 8 0 1 6 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 33 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range (c ) package description package option adum540 1arwz 3 1 1 100 40 ?40 to +105 16 - lead soic_w rw -16 adum540 1crwz 3 1 25 60 6 ?40 to +105 16 - lead soic_w rw -16 adum540 2arwz 2 2 1 100 40 ?40 to +105 16 - lead soic_w rw -16 adum540 2crwz 2 2 25 60 6 ?40 to +105 16 - lead soic_w rw -16 adum540 3arwz 1 3 1 100 40 ?40 to +105 16 - lead soic_w rw -16 adum540 3crwz 1 3 25 60 6 ?40 to +105 16 - lead soic_w rw -16 adum540 4arwz 0 4 1 100 40 ?40 to +105 16 - lead soic_w rw -16 adum540 4crwz 0 4 25 60 6 ?40 to +105 16 - lead soic_w rw -16 1 z = rohs compliant part. 2 tape and reel are available. the addition of an rl suffix designates a 13 (1,000 units) tape and reel option.
data sheet adum5401/adum5402/adum5403/adum5404 rev. c | page 27 of 28 notes
adum5401/adum5402/adum5403/adum5404 data sheet rev. c | page 28 of 28 notes ? 2008 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06577 - 0- 6/12(c)

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